(1) Field of the Invention
This invention relates to a method for in-situ checking of the overlay accuracy of two masks used in two levels of an integrated circuit wafer.
(2) Description of the Related Art
In photolithographic processing of integrated circuit wafers typically each layer is processed after exposing a pattern on that layer using a mask. It is, of course, of great importance that the alignment of each mask to the wafer, and thus to all other layers processed, is accurate. Often overlay patterns located on the different masks are used to measure the alignment accuracy between two layers. FIGS. 1 and 2 show a box in box pattern used to measure alignment between two layers. FIG. 1 shows the top view of a wafer 100 showing the box in box pattern formed on the wafer. FIG. 1 shows the outer box 140, with the inner perimeter 141 of the outer box 140 indicated by a dashed line, and the inner box 180, with the outer perimeter 181 of the inner box 180 indicated by a solid line.
FIG. 2 shows a cross section view of the wafer 100 shown in FIG. 1 taken along line 2–2′ of FIG. 1. As shown in FIG. 2 the outer box 140 is formed by a patterned layer of metal formed on the substrate 120. A layer of material such as an insulator 160 is typically formed over the patterned layer of metal forming the outer box 140. The inner box 180 is formed by an exposed and developed layer of photoresist. The position of the inner box 180 relative to the outer box 140 can be measured to determine the alignment accuracy. This method will necessarily require two photoprocessing steps, with two photoresist application, exposure, and developing steps. One photoprocessing step is required to form the outer box 140 and one to form the inner box 180.
U.S. Pat. No. 5,498,500 to Bae describes an overlay measurement mark and method of measuring an overlay error between three patterns in a semiconductor device.
U.S. Pat. No. 5,635,336 to Bae describes the use of a box in box overlay pattern using a grove formed at the inner perimeter of the outer box to improve the measurement accuracy.
U.S. Pat. No. 5,770,338 to Lim et al. describes a phase shifting overlay mark that measures exposure energy and focus.
U.S. Pat. No. 6,330,355 to Chen et al. describes an overlay layout and method for determining the overlay accuracy of a first chip image relative to a second chip image when the first and second chip images are used to form a single layer on a single chip.